We want to implement the two logic functions given by F = A + B + C and G=A+ B +

We want to implement the two logic functions given by F = A + B + C and G=A+ B + C + D. (I) Implement these functions using domino logic as cascaded stages so as to minimize the total transistor count. (ii) Design an np-CMOS implementation of the same
logic functions. Assume both true and complementary signals are available.